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base repository: sailfishos-mirror/llvm-project
base: 1f169a774cb865659cefe085e70a56a884e3711e
head repository: sailfishos-mirror/llvm-project
compare: 7fab1146e42ca76a78cccd0aa274168c628d01de
- 15 commits
- 108 files changed
- 13 contributors
Commits on Jun 30, 2021
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[clang] Fix UB when string.front() is used for the empty string
Compilation database might have empty string as a command line argument. But ExpandResponseFilesDatabase::expand doesn't expect this and assumes that string.front() can be used for any argument. It is undefined behaviour if string is empty. With debug build mode it causes crash in clangd. Test Plan: check-clang Differential Revision: https://reviews.llvm.org/D105120
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Recommit "[AArch64] Custom lower <4 x i8> loads"
This recommits D104782 including a fix for adding a wrong operand to the new load node. Differential Revision: https://reviews.llvm.org/D105110
Sjoerd Meijer committedJun 30, 2021 -
[mlir][llvm] Add a test for memref.copy lowering to llvm
This was missing and also there was a bug in the lowering itself, which went unnoticed due to it. Differential Revision: https://reviews.llvm.org/D105122
Stephan Herhut committedJun 30, 2021 -
[ARM][NFC] Remove an unused method
`ARMInstPrinter::printMveAddrModeQOperand()` was added in D62680, but was never used. It looks like `printT2AddrModeImm8Operand<false>()` is used instead. Differential Revision: https://reviews.llvm.org/D105124
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[mlir][linalg][python] Explicit shape and dimension order in OpDSL.
Extend the OpDSL syntax with an optional `domain` function to specify an explicit dimension order. The extension is needed to provide more control over the dimension order instead of deducing it implicitly depending on the formulation of the tensor comprehension. Additionally, the patch also ensures the symbols are ordered according to the operand definitions of the operation. Differential Revision: https://reviews.llvm.org/D105117
Tobias Gysi committedJun 30, 2021 -
[ARMInstPrinter] Print the target address of a branch instruction
This follows other patches that changed printing immediate values of branch instructions to target addresses, see D76580 (x86), D76591 (PPC), D77853 (AArch64). As observing immediate values might sometimes be useful, they are printed as comments for branch instructions. // llvm-objdump -d output (before) 000200b4 <_start>: 200b4: ff ff ff fa blx #-4 <thumb> 000200b8 <thumb>: 200b8: ff f7 fc ef blx #-8 <_start> // llvm-objdump -d output (after) 000200b4 <_start>: 200b4: ff ff ff fa blx 0x200b8 <thumb> @ imm = #-4 000200b8 <thumb>: 200b8: ff f7 fc ef blx 0x200b4 <_start> @ imm = #-8 // GNU objdump -d. 000200b4 <_start>: 200b4: faffffff blx 200b8 <thumb> 000200b8 <thumb>: 200b8: f7ff effc blx 200b4 <_start> Differential Revision: https://reviews.llvm.org/D104701
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[TableGen] Allow identical MnemonicAliases with no predicate
My use case for this is illustrated in the test case: I want to define the same instruction twice with different (disjoint) predicates, because the instruction has different operands on different subtargets. It's convenient to do this with a multiclass that also defines an alias for the instruction. Previously tablegen would complain if this alias was defined twice with no predicate. One way to fix this would be to add a predicate on each definition of the alias, matching the predicate on the instruction. But this (a) is slightly awkward to do in the real world use case I had, and (b) leads to an inefficient matcher that will do something like this: if (Mnemonic == "foo_alias") { if (Features.test(Feature_Subtarget1Bit)) Mnemonic == "foo"; else if (Features.test(Feature_Subtarget2Bit)) Mnemonic == "foo"; return; } It would be more efficient to skip the feature tests and return "foo" unconditionally. Overall it seems better to allow multiple definitions of the identical alias with no predicate. Differential Revision: https://reviews.llvm.org/D105033
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[MTE] Remove redundant helper function.
Looking at PostDominatorTree::dominates, we can see that has the same logic (with the addition of handling Phi nodes - which are not used as inputs in this pass) as the helper function. Reviewed By: eugenis Differential Revision: https://reviews.llvm.org/D105141
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[NFC] Rename shadowed variable in InnerLoopVectorizer::createInductio…
…nVariable Avoid creating a IRBuilder stack variable with the same name as the class member.
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[hwasan] Make sure we retag with a new tag on free.
Reviewed By: eugenis Differential Revision: https://reviews.llvm.org/D105021
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[ConstantRanges] Use APInt for constant case for urem/srem.
Currently UREM & SREM on constant ranges produces overly pessimistic results for single element constant ranges. Delegate to APInt's implementation if both operands are single element constant ranges. We already do something similar for other binary operators, like binary AND. Fixes PR49731. Reviewed By: lebedev.ri Differential Revision: https://reviews.llvm.org/D105115
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[AMDGPU] Simplify getReservedNumSGPRs
This is a followup patch on D103636 where it seemed checking on amdgpu-calls and amdgpu-stack-objects is unnecessary. Removing these checks didn't regress any tests functionally. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D104513
madhur13490 authored and madhur13490 committedJun 30, 2021 -
[clang] NFC: add line break at the end of if expressions
Hi, In function TransformTemplateArgument, would it be better to add line break at the end of "if" expressions? I use clang-format to do the job for me. Thanks a lot Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D104604
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[OPENMP]Fix PR50929: Ignored initializer clause in user-defined reduc…
…tion. No need to try to create the default constructor for private copy, it will be called automatically in the initializer of the declare reduction. Fixes balance between constructors/destructors calls. Differential Revision: https://reviews.llvm.org/D105143
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