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Squashed 'qtwebkit/' changes from 1e4dd58..5e64d7e
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5e64d7e TextureMapperGL must take hiDPI transform into account
247ab7f Fix transform of accelerated layers on hiDPI painters
f314bb4 Fix assert in m_stack.isEmpty() in GraphicsContext::~GraphicsContext()
db006e7 Fix assert in BitmapTextureImageBuffer::applyFilters()
beb21ff Fix RenderGeometryMap.cpp ASSERT on Google Plus
1bedb01 Don't pollute .prl & .pc files with private dependencies
b7d359c Apply device pixel ratio to transparency layers
64a4dc7 Forward devicePixelRatio to WebCore Page
f5d7c69 Do not notifyFinished on resources never loaded
5535b40 Make sure the correct position for the plugin is used when showing
4fad6da Merge remote-tracking branch 'origin/release' into stable
231d3a1 Bump MODULE_VERSION to 5.2.2
99113b7 Reduce memory footprint when linking
4c10389 Ensure that cursor rectangle is always valid.
9b0de4a Check also for mingw-g++-xxx specs
a368034 Reapply mouse event handling in QQuickWebViewFlickablePrivate.
d92f0c4 [Qt] Re-enable plugins on Mac.
3fdcf78 Use pkg-config to build against ICU
9215ead Remove dependency v8-private
a677526 Extend disabling of whole-program-optimizations to MSVC 2013
d0306ff ASSERTION FAILED: m_repaintRect == renderer().clippedOverflowRectForRepaint(renderer().containerForRepaint()) after r135816
9ecc1d5 OS X Mavericks/Xcode5: Find libxslt and libxml2 headers
a038352 Do not accept all touch events
3bb9504 [texmap] Borders on rotating images are hidden/wrongly rendered with edge distance antialiasing
8a716a2 Fix QtWebKit build on ARM softfp
fa132a4 Do not completely erase LIBS variable
2573bb6 Do not try to build QtWebKit as a static library
40c371c Merge "Merge remote-tracking branch 'origin/release' into stable" into refs/staging/stable
f709870 Merge remote-tracking branch 'origin/release' into stable
8d01037 Revert "[EFL][WK2] Never create WebCore scrollbars for EFL/WK2"
4f8a92b Fix scroll-bar behavior in RTL layout
9bd1e4c Apply size constraints for direct compositing also to background images.
7122e75 Handle PlatformPageClient not being set in Windows PluginView.
4ef1b43 Doc: Update WebView code sample on Qt WebKit landing page
4c86230 Do not force SSE2 instructions on i386 builds
27f087d Remove superfluous assert from WebKitQmlPlugin::initializeEngine
a3b20f8 Fix crash on exit of Google Maps
48c1382 Fix bad if test in QQuickWebViewPrivate::didFailLoad.
155ec22 Merge remote-tracking branch 'origin/release' into stable
cc83829 Bump MODULE_VERSION to 5.2.1
840e281 Account for when the QGraphicsView is a top level widget
a7084bf WebKitQML examples does not work on Mac
159d685 Make qtwebkit disable itself if the gui module isn't present.
fb02f6e Doc: Fix issues in Qt WebKit documentation config file
8d3a152 Detach image data when returning an ImageFrame as a native image.
21d9ab6 [sh4] Fix revertJumpReplacementToBranchPtrWithPatch in MacroAssembler.
b16a154 [sh4] Protect repatchCompact from flushConstantPool.
d7af109 [sh4] Fix load32WithUnalignedHalfWords function in baseline JIT.
966168b [sh4] Refactor jumps in baseline JIT to return label after the jump.
cd3b33a Fix performance regression in HTML5 canvas stroke()
0224bf8 Fix compilation on ARM
cf6684e Merge remote-tracking branch 'origin/release' into stable
bf8e1a5 Fix left-over reference to qtlocation
bb0355b Fix crash when converting QObjectList
b12852d Fix MSVC2013 compilation
c317e5d Add padding objects for classes with netscape plugin api conditionals.
049fcfb Trigger layout after resizing the FrameView.
92e8d60 [GStreamer] cannot play live streams
45ccf87 Do no check seek offset against internal size on gstreamer source element
8c7a760 Fix fullscreen support with GStreamer
dddffca Fix compilation of GraphicsSurfaceMac on OS X 10.9 Mavericks
1511044 Disable QtWebkit for QNX
5102ba6 Fix ABI violation in QWebSettings::CSSCompositingEnabled
a3e3255 Remove unused runtime enabled features
419af54 Prospective build fix for builds with video disabled
0628508 Support HTML5 media context menu items
36321b9 Load libudev at run-time
42f59b1 Redisable debug-info on MinGW64
92a17ec Only use 64bit atomics when supported
f65ce03 ASSERTION FAILED: !node || node->isShadowRoot() in WebCore::EventRetargeter::eventTargetRespectingTargetRules
e0e98ce Fix NULL de-refernce in HTMLAnchorElement::sendPings when settings doesn't exist
d4a6abc Fix build for boot2qt eAndroid
2761751 Use global Qt configuration for libudev
ff54f45 Update configure warnings
d12387d Build improvements
8591d12 [sh4] Jump over maxJumpReplacementSize in revertJumpToMove.
2e6916a [arm] Inverted src and dest FP registers in DFG speculative JIT when using hardfp.
c075f08 SVG stroke-dasharray not working
3909ae8 Revert r152209
6d6a120 32-bit code gen for TypeOf doesn't properly update the AbstractInterpreter state
332de74 Fix undefined reference linker errors with MinGW
7082885 Missing QWebSettings
686c380 Define use_glib in features.prf
4354f29 REGRESSION (r149928): CanvasStyle::operator= leaks everything
23e9d9d Fix build with GStreamer on non-linux X11 platforms
f6069ba Improve backtraces on linux 64bit
94a1886 Enable more AllInOne files
73ca371 Remove unused WebKit2QML library
1cb89af [Qt] SHOULD NEVER BE REACHED is touched WebCore::InputType::createStepRange
1841b19 Enable more AllInOne files
ca98274 Warning on starting WebProcess
265d717 Revert "Fix debug builds for Windows32 x86 bots."
85378c3 Fix linux-clang with clang 3.4
29ca4c5 Crash on GeoLocation demo
7d9d4f0 Fix debug builds for Windows32 x86 bots.
008aa4c [sh4] Missing instruction in nativeCallTrampoline LLINT function.

git-subtree-dir: qtwebkit
git-subtree-split: 5e64d7e
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Raine Makelainen committed Feb 6, 2014
1 parent 8b9706e commit ca824ea
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Showing 131 changed files with 1,010 additions and 823 deletions.
2 changes: 1 addition & 1 deletion .qmake.conf
View file
Expand Up @@ -3,4 +3,4 @@ MODULE_QMAKE_OUTDIR = $$shadowed($$PWD/Tools/qmake)
QMAKEPATH += $$PWD/Tools/qmake $$MODULE_QMAKE_OUTDIR
load(qt_build_config)

MODULE_VERSION = 5.2.0
MODULE_VERSION = 5.2.2
1 change: 0 additions & 1 deletion Source/JavaScriptCore/LLIntOffsetsExtractor.pro
View file
Expand Up @@ -18,7 +18,6 @@ debug_and_release {
INCLUDEPATH += $$QT.core.includes
CONFIG += console
CONFIG -= qt
LIBS =

defineTest(addIncludePaths) {
# Just needed for include paths
Expand Down
14 changes: 13 additions & 1 deletion Source/JavaScriptCore/assembler/MacroAssemblerARM.cpp
View file
Expand Up @@ -36,7 +36,19 @@
#include <fcntl.h>
#include <unistd.h>
#include <elf.h>
#include <asm/hwcap.h>
# if OS(ANDROID) && PLATFORM(QT)
# include <asm/procinfo.h>
typedef struct
{
uint32_t a_type;
union
{
uint32_t a_val;
} a_un;
} Elf32_auxv_t;
# else
# include <asm/hwcap.h>
# endif
#endif

namespace JSC {
Expand Down
33 changes: 14 additions & 19 deletions Source/JavaScriptCore/assembler/MacroAssemblerSH4.h
View file
Expand Up @@ -1312,15 +1312,15 @@ class MacroAssemblerSH4 : public AbstractMacroAssembler<SH4Assembler> {
void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
{
RegisterID scr = claimScratch();
RegisterID scr1 = claimScratch();
Jump m_jump;
JumpList end;

loadEffectiveAddress(address, scr);

RegisterID scr1 = claimScratch();
if (dest != SH4Registers::r0)
move(SH4Registers::r0, scr1);

loadEffectiveAddress(address, scr);

m_assembler.ensureSpace(m_assembler.maxInstructionSize + 58, sizeof(uint32_t));
move(scr, SH4Registers::r0);
m_assembler.testlImm8r(0x3, SH4Registers::r0);
Expand Down Expand Up @@ -1452,10 +1452,9 @@ class MacroAssemblerSH4 : public AbstractMacroAssembler<SH4Assembler> {
m_assembler.dcmppeq(right, right);
takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppeq(left, right);
Jump m_jump = Jump(m_assembler.je());
m_assembler.branch(BF_OPCODE, 2);
takeBranch.link(this);
m_assembler.extraInstrForBranch(scratchReg3);
return m_jump;
return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}

if (cond == DoubleGreaterThanOrUnordered) {
Expand All @@ -1466,10 +1465,9 @@ class MacroAssemblerSH4 : public AbstractMacroAssembler<SH4Assembler> {
m_assembler.dcmppeq(right, right);
takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppgt(right, left);
Jump m_jump = Jump(m_assembler.je());
m_assembler.branch(BF_OPCODE, 2);
takeBranch.link(this);
m_assembler.extraInstrForBranch(scratchReg3);
return m_jump;
return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}

if (cond == DoubleGreaterThanOrEqualOrUnordered) {
Expand All @@ -1485,10 +1483,9 @@ class MacroAssemblerSH4 : public AbstractMacroAssembler<SH4Assembler> {
m_assembler.dcmppeq(right, right);
takeBranch.append(Jump(m_assembler.jne(), SH4Assembler::JumpNear));
m_assembler.dcmppgt(left, right);
Jump m_jump = Jump(m_assembler.je());
m_assembler.branch(BF_OPCODE, 2);
takeBranch.link(this);
m_assembler.extraInstrForBranch(scratchReg3);
return m_jump;
return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}

if (cond == DoubleLessThanOrEqualOrUnordered) {
Expand All @@ -1504,17 +1501,15 @@ class MacroAssemblerSH4 : public AbstractMacroAssembler<SH4Assembler> {
Jump branchTrue()
{
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 6, sizeof(uint32_t));
Jump m_jump = Jump(m_assembler.je());
m_assembler.extraInstrForBranch(scratchReg3);
return m_jump;
m_assembler.branch(BF_OPCODE, 2);
return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}

Jump branchFalse()
{
m_assembler.ensureSpace(m_assembler.maxInstructionSize + 6, sizeof(uint32_t));
Jump m_jump = Jump(m_assembler.jne());
m_assembler.extraInstrForBranch(scratchReg3);
return m_jump;
m_assembler.branch(BT_OPCODE, 2);
return Jump(m_assembler.extraInstrForBranch(scratchReg3));
}

Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
Expand Down Expand Up @@ -2430,7 +2425,7 @@ class MacroAssemblerSH4 : public AbstractMacroAssembler<SH4Assembler> {

static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel instructionStart, RegisterID rd, void* initialValue)
{
SH4Assembler::revertJumpToMove(instructionStart.dataLocation(), rd, reinterpret_cast<int>(initialValue));
SH4Assembler::revertJumpReplacementToBranchPtrWithPatch(instructionStart.dataLocation(), rd, reinterpret_cast<int>(initialValue));
}

static CodeLocationLabel startOfPatchableBranchPtrWithPatchOnAddress(CodeLocationDataLabelPtr)
Expand Down
152 changes: 56 additions & 96 deletions Source/JavaScriptCore/assembler/SH4Assembler.h
View file
Expand Up @@ -1241,19 +1241,19 @@ class SH4Assembler {
{
RegisterID scr = claimScratch();
m_buffer.ensureSpace(maxInstructionSize + 4, sizeof(uint32_t));
AssemblerLabel label = m_buffer.label();
loadConstantUnReusable(0x0, scr);
branch(BRAF_OPCODE, scr);
nop();
releaseScratch(scr);
return label;
return m_buffer.label();
}

void extraInstrForBranch(RegisterID dst)
AssemblerLabel extraInstrForBranch(RegisterID dst)
{
loadConstantUnReusable(0x0, dst);
branch(BRAF_OPCODE, dst);
nop();
nop();
return m_buffer.label();
}

AssemblerLabel jmp(RegisterID dst)
Expand All @@ -1271,23 +1271,20 @@ class SH4Assembler {

AssemblerLabel jne()
{
AssemblerLabel label = m_buffer.label();
branch(BF_OPCODE, 0);
return label;
return m_buffer.label();
}

AssemblerLabel je()
{
AssemblerLabel label = m_buffer.label();
branch(BT_OPCODE, 0);
return label;
return m_buffer.label();
}

AssemblerLabel bra()
{
AssemblerLabel label = m_buffer.label();
branch(BRA_OPCODE, 0);
return label;
return m_buffer.label();
}

void ret()
Expand Down Expand Up @@ -1361,33 +1358,16 @@ class SH4Assembler {
{
ASSERT(from.isSet());

uint16_t* instructionPtr = getInstructionPtr(code, from.m_offset);
uint16_t instruction = *instructionPtr;
uint16_t* instructionPtr = getInstructionPtr(code, from.m_offset) - 3;
int offsetBits = (reinterpret_cast<uint32_t>(to) - reinterpret_cast<uint32_t>(code)) - from.m_offset;

if (((instruction & 0xff00) == BT_OPCODE) || ((instruction & 0xff00) == BF_OPCODE)) {
/* BT label ==> BF 2
nop LDR reg
nop braf @reg
nop nop
*/
offsetBits -= 8;
instruction ^= 0x0202;
*instructionPtr++ = instruction;
changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
*instructionPtr = instruction;
printBlockInstr(instructionPtr - 2, from.m_offset, 3);
return;
}

/* MOV #imm, reg => LDR reg
braf @reg braf @reg
nop nop
*/
/* MOV #imm, reg => LDR reg
braf @reg braf @reg
nop nop
*/
ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE);
changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 6);
changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
printInstr(*instructionPtr, from.m_offset + 2);
}

Expand Down Expand Up @@ -1473,10 +1453,17 @@ class SH4Assembler {

static void repatchCompact(void* where, int32_t value)
{
uint16_t* instructionPtr = reinterpret_cast<uint16_t*>(where);
ASSERT(value >= 0);
ASSERT(value <= 60);
*reinterpret_cast<uint16_t*>(where) = ((*reinterpret_cast<uint16_t*>(where) & 0xfff0) | (value >> 2));
cacheFlush(reinterpret_cast<uint16_t*>(where), sizeof(uint16_t));

// Handle the uncommon case where a flushConstantPool occurred in movlMemRegCompact.
if ((instructionPtr[0] & 0xf000) == BRA_OPCODE)
instructionPtr += (instructionPtr[0] & 0x0fff) + 2;

ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFRM_OPCODE);
instructionPtr[0] = (instructionPtr[0] & 0xfff0) | (value >> 2);
cacheFlush(instructionPtr, sizeof(uint16_t));
}

static void relinkCall(void* from, void* to)
Expand All @@ -1490,24 +1477,10 @@ class SH4Assembler {
static void relinkJump(void* from, void* to)
{
uint16_t* instructionPtr = reinterpret_cast<uint16_t*> (from);
uint16_t instruction = *instructionPtr;
int32_t offsetBits = (reinterpret_cast<uint32_t>(to) - reinterpret_cast<uint32_t>(from));

if (((*instructionPtr & 0xff00) == BT_OPCODE) || ((*instructionPtr & 0xff00) == BF_OPCODE)) {
offsetBits -= 8;
instructionPtr++;
ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
*instructionPtr = instruction;
printBlockInstr(instructionPtr, reinterpret_cast<uint32_t>(from) + 1, 3);
cacheFlush(instructionPtr, sizeof(SH4Word));
return;
}

instructionPtr -= 3;
ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE);
changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 6);
printInstr(*instructionPtr, reinterpret_cast<uint32_t>(from));
changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(to) - reinterpret_cast<uint32_t>(from));
}

// Linking & patching
Expand All @@ -1520,9 +1493,13 @@ class SH4Assembler {
static void replaceWithJump(void *instructionStart, void *to)
{
SH4Word* instruction = reinterpret_cast<SH4Word*>(instructionStart);
intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + 2 * sizeof(SH4Word));
intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + 3 * sizeof(SH4Word));

if ((instruction[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE) {
// We have an entry in constant pool and we potentially replace a branchPtrWithPatch, so let's backup what would be the
// condition (CMP/xx and Bx opcodes) for later use in revertJumpReplacementToBranchPtrWithPatch before putting the jump.
instruction[4] = instruction[1];
instruction[5] = instruction[2];
instruction[1] = (BRAF_OPCODE | (instruction[0] & 0x0f00));
instruction[2] = NOP_OPCODE;
cacheFlush(&instruction[1], 2 * sizeof(SH4Word));
Expand All @@ -1533,30 +1510,34 @@ class SH4Assembler {
cacheFlush(instruction, 3 * sizeof(SH4Word));
}

changePCrelativeAddress(instruction[0] & 0x00ff, instruction, difference - 2);
changePCrelativeAddress(instruction[0] & 0x00ff, instruction, difference);
}

static void revertJumpToMove(void* instructionStart, RegisterID rd, int imm)
static void revertJumpReplacementToBranchPtrWithPatch(void* instructionStart, RegisterID rd, int imm)
{
SH4Word *insn = reinterpret_cast<SH4Word*>(instructionStart);
ASSERT((insn[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);

if ((insn[1] & 0xf000) == CMPEQ_OPCODE) {
insn[0] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, SH4Registers::r13, insn[0] & 0x00ff);
ASSERT((insn[0] & 0x00ff) != 1);

insn[0] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, SH4Registers::r13, insn[0] & 0x00ff);
if ((insn[1] & 0xf0ff) == BRAF_OPCODE) {
insn[1] = (insn[4] & 0xf00f) | (rd << 8) | (SH4Registers::r13 << 4); // Restore CMP/xx opcode.
insn[2] = insn[5];
ASSERT(((insn[2] & 0xff00) == BT_OPCODE) || ((insn[2] & 0xff00) == BF_OPCODE));
ASSERT((insn[3] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
insn[4] = (BRAF_OPCODE | (insn[3] & 0x0f00));
insn[5] = NOP_OPCODE;
cacheFlush(insn, 6 * sizeof(SH4Word));
} else {
// The branchPtrWithPatch has already been restored, so we just patch the immediate value and ASSERT all is as expected.
ASSERT((insn[1] & 0xf000) == 0x3000);
insn[1] = (insn[1] & 0xf00f) | (rd << 8) | (SH4Registers::r13 << 4);
cacheFlush(insn, 2 * sizeof(SH4Word));
changePCrelativeAddress(insn[0] & 0x00ff, insn, imm);
return;
ASSERT(((insn[2] & 0xff00) == BT_OPCODE) || ((insn[2] & 0xff00) == BF_OPCODE));
ASSERT((insn[3] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
ASSERT(insn[5] == NOP_OPCODE);
}

if ((insn[0] & 0x00ff) == 1)
insn[1] = getOpcodeGroup6(BRA_OPCODE, 3);
else
insn[1] = NOP_OPCODE;

insn[2] = NOP_OPCODE;
cacheFlush(&insn[1], 2 * sizeof(SH4Word));

changePCrelativeAddress(insn[0] & 0x00ff, insn, imm);
}

Expand All @@ -1565,48 +1546,27 @@ class SH4Assembler {
ASSERT(to.isSet());
ASSERT(from.isSet());

uint16_t* instructionPtr = getInstructionPtr(data(), from.m_offset);
uint16_t instruction = *instructionPtr;
int offsetBits;
uint16_t* instructionPtr = getInstructionPtr(data(), from.m_offset) - 1;
int offsetBits = (to.m_offset - from.m_offset);

if (type == JumpNear) {
int offset = (codeSize() - from.m_offset) - 4;
uint16_t instruction = instructionPtr[0];
int offset = (offsetBits - 2);
ASSERT((((instruction == BT_OPCODE) || (instruction == BF_OPCODE)) && (offset >= -256) && (offset <= 254))
|| ((instruction == BRA_OPCODE) && (offset >= -4096) && (offset <= 4094)));
*instructionPtr++ = instruction | (offset >> 1);
printInstr(*instructionPtr, from.m_offset + 2);
return;
}

if (((instruction & 0xff00) == BT_OPCODE) || ((instruction & 0xff00) == BF_OPCODE)) {
/* BT label => BF 2
nop LDR reg
nop braf @reg
nop nop
*/
offsetBits = (to.m_offset - from.m_offset) - 8;
instruction ^= 0x0202;
*instructionPtr++ = instruction;
if ((*instructionPtr & 0xf000) == MOVIMM_OPCODE) {
uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress());
*addr = offsetBits;
} else
changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
*instructionPtr = instruction;
printBlockInstr(instructionPtr - 2, from.m_offset, 3);
return;
}

/* MOV # imm, reg => LDR reg
braf @reg braf @reg
nop nop
*/
ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE);
offsetBits = (to.m_offset - from.m_offset) - 6;
instructionPtr -= 2;
ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE);

instruction = *instructionPtr;
if ((instruction & 0xf000) == MOVIMM_OPCODE) {
if ((instructionPtr[0] & 0xf000) == MOVIMM_OPCODE) {
uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress());
*addr = offsetBits;
printInstr(*instructionPtr, from.m_offset + 2);
Expand Down
1 change: 1 addition & 0 deletions Source/JavaScriptCore/bytecode/ArrayProfile.cpp
View file
Expand Up @@ -24,6 +24,7 @@
*/

#include "config.h"
#include "JSCellInlines.h"
#include "ArrayProfile.h"

#include "CodeBlock.h"
Expand Down
1 change: 1 addition & 0 deletions Source/JavaScriptCore/bytecode/PreciseJumpTargets.cpp
View file
Expand Up @@ -24,6 +24,7 @@
*/

#include "config.h"
#include "JSCellInlines.h"
#include "PreciseJumpTargets.h"

namespace JSC {
Expand Down

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